The trend of semiconductor packages is always developing toward thinner, lighter, shorter, and smaller with the requirement of cost reduction. Bonding pads of conventional semiconductor chips are used as external electrodes where bonding wires are used to electrically connect a chip to a substrate. However, the bonding wires have a loop height. As shown in FIG. 1, metal wires formed by wire bonding are implemented as electrical connections in a conventional package structure 1 such as FBGA or window BGA where a substrate 100 serves as a chip carrier with internal electrical connections. The substrate 100 with internal circuitry (not shown in the figure) has a top surface 111, a bottom surface 112, and a slot 113. A plurality of external pads 114 are disposed on the bottom surface 112 for disposing a plurality of external terminals 50 such as solder balls. The active surface 111 of a chip 10 is attached to the top surface 111 of the substrate 100 through a die-attaching layer 20 such as epoxy, adhesive paste or a film with the bonding pads 12 disposed on the active surface 11 exposed from and aligned in the slot 113. A plurality of metal wires 30 formed by wire bonding pass through the slot 113 to electrically connect the bonding pads 12 of the chip 10 to internal fingers of the substrate 100. An encapsulant 40 is implemented to encapsulate the chip 10 and the metal wires 30 except the external pads 114 to avoid external contaminations. The external terminals 50 are disposed on the external pads 114 as external soldering points.
Since metal wires 30 formed by wire bonding are implemented in the conventional FBGA package 1 as electrical connections between the chip 10 and the substrate 100 where each metal wire 30 has two metal bonding interfaces with a higher loop height leading to signal delay which is not suitable for high-frequency IC packages, especially for DDR3 or IC packages with operation frequencies more than 500 MHz.
As shown in FIG. 2, inner leads built in a substrate are implemented as electrical connections in another conventional package 2 such as a micro-BGA package where a substrate 200 serves as a chip carrier with internal electrical connections. The substrate 200 is a wiring board with a thinner thickness such as a flexible film. The substrate 200 includes a substrate core 210, a first trace 220, and a second trace 230. The substrate core 210 has a slot 213 and a first board part 214 and a second board part 215 located at two opposing sides of the slot 213 where the slot 213 penetrates through and locates at the center the substrate core 210. The first trace 220 is disposed on the first board part 214 and has a suspended inner lead 221 extended into the slot 213 where the inner lead 221 is the suspended integral part of the first trace 220 which is normally made of copper and is an internal component of the substrate 200. Furthermore, as shown in FIG. 2, the substrate core 210 further has a top surface 211 and a bottom surface 212 where a plurality of external pads 226 are disposed on the bottom surface 212 and electrically connected with the corresponding first trace 220. A solder mask 240 is formed on the bottom surface 212 of the substrate core 210 to cover the first trace 220 and the second trace 230 with the inner leads 221 and the external pads 226 exposed.
As shown in FIG. 2 again, the active surface 11 of a chip 10 is attached to the substrate 200, i.e., the top surface 211 of the substrate core 210, through an elastomer 250 with the bonding pads 12 exposed from and aligned in the slot 213. The inner lead 221 is then bent through the slot 213 and thermally bonded to the bonding pads 12 of the chip 10 through conventional ILB (Inner Lead Bonding) without any extra components for external electrical connections such as metal wires formed by wire bonding to electrically connect the chip 10 to the substrate 200 where there is no loop height with only one metal bonding interface from bonding pads of the chip to the circuitry of a substrate so that the signal path can be shortened for high-frequency IC packages. An encapsulant 40 is implemented to encapsulate the chip 10 and the inner leads 221 to avoid external contaminations. A plurality of external terminals 50 such as solder balls are then disposed on the external pads 226 of the substrate 200 as external soldering points.
Since the inner leads 221 are suspended in the slot 213, the inner leads 221 need firmly fixed before assembly to avoid sweeping and misalignment. As shown in FIG. 3A, the inner lead 221 has an assumed broken point 222. The second trace 230 is disposed on the second board part 215 and is integrally connected to the inner leads 221 at the assumed broken point 222 to achieve fixing of the inner leads 221 before bonding. In order to enhance easy breaking of the inner leads 221 at the assumed broken point 222, two symmetric V-notches 224 are formed at two corresponding external sides of the inner leads 221 so that the width W1 of the assumed broken point 222 is smaller than the width W of the inner lead 221.
As shown in FIG. 3B, thermal compression of the inner lead 221 is illustrated where a thermal-compression bonding head 60 is aligned to and pressed at the assumed bonding location 225 defined on the inner lead 221 to bond the inner lead 221 to the bonding pad 12. During thermal compression bonding processes, the inner lead 221 is expected to break at the assumed broken point 222 to form an ideal crack from the upper V-notches 224 to the lower V-notch 224. However, the crack at the assumed broken point 222 after thermal compression in actual operation is irregular and not easy to break. Therefore, in order to prevent irregular breaking of the assumed broken point 222, the assumed broken point 222 is disposed close to the assumed bonding location 225 and the depth of the V-notches 224 has to be increased, i.e., to reduce the width of W1. However, the assumed broken point 222 becomes a stress concentrated point and is easily broken at the unexpected time such as shipping or operation. Furthermore, when the assumed broken point 222 is too close to from the assumed bonding location 225, the thicknesses of the substrate 200 and the elastomer 250 will impact the effective bonding area of the inner leads 221 to the bonding pads 12 leading to poor thermal-compression bonding.